The present disclosure relates to a nonvolatile cache memory, a processing method of the nonvolatile cache memory, and a computer system having the nonvolatile cache memory.
In a known computer system, a processor acquires data and information such as a command from a main memory or updates the information of the main memory. At this time, accessing performance such as the latency of the main memory is inferior to the processing performance of the processor. Therefore, a difference in the performance between the main memory and the processor causes a bottleneck to the total performance of the computer system.
A cache memory is a memory newly provided in a storage layer to eliminate the bottleneck and arranged between the processor and the main memory.
In general, a SRAM (Static Random Access Memory) that operates at higher speed than the main memory is used as the cache memory.
When the processor acquires the data from the main memory or updates the information of the main memory, the same data is also stored in the cache memory. Next, when the same data is acquired or updated, the high-speed cache memory performs the input and output of the data instead of the main memory. Thus, the difference in the performance between the main memory and the processor is covered up, whereby the high-speed computer system is constructed.
Meanwhile, in order to apply a computer system to mobile equipment, there is an increasing demand for a power saving control technology. In a semiconductor circuit technology used in the latest high performance processor, a ratio of a leakage current to power consumption is large. Therefore, there has been used a technology so-called power gating to interrupt power supply to a processor to prevent a leakage current from occurring, for example, when there is no command to be processed.
On the other hand, a SRAM used as a cache memory is a volatile memory. Therefore, data stored in the SRAM is lost as the power supply is interrupted. In view of the problem, Japanese Patent Application Laid-open No. 2011-150653 discloses a method of interrupting power supply only to a controller that controls the input and output of data while retaining the power supply to a SRAM cell array that stores the data among parts constituting a cache memory to reduce power consumed in the cache memory.